CH7521A

特征

General

l Compliant with DisplayPort specification version 1.2 and Embedded DisplayPort (eDP) specification version 1.2

l Support VESA and CEA timing standards up to 7680x1080@60Hz or 4800x2160@60Hz with 8/10 bit graphic color depth

l Support Single Port, Dual Ports , Quad ports and Six ports LVDS output interface

l Crystal Free

l Built in self test mode support

l Hot Plug Detection

l Support dithering from 10 bit to 8 bit and 8-bit+ FRC

l Region CRC checking support

l Black panel or Color Bar during invalid input and failure detection

l 15-pixel overlap on the Left and Right sides support, and enabled by the internal register

l Initiated and controlled by firmware which is loaded from External BOOT ROM automatically upon power up

l integrated EDID Buffer up to 2 blocks

l Firmware updated through I2C slave or AUX Channel

l I2C slave support up to 400K Hz

l Programmable power management

l Achieve bit error rate <10-9 for raw transport data per lane and symbol error rate <10-12 for control data

l Low power consumption

l ESD HBM 4KV

l Offered in a 128-pin QFN package (12.5 x 12.5mm)

描述

Chrontel’s CH7521A is a low-cost, low-power semiconductor device that translates the DisplayPort signal to the LVDS in form of RGB. This innovative DisplayPort receiver with integrated 6 channel LVDS transmitters is specially designed to target the Pro-AV and Automotive market segments. Leveraging the DisplayPort’s unique source/sink “Link Training” routine, the CH7521A is capable of instantly bring up the video display to the LCD when the initialization process is completed between CH7521A and the graphic chip.

The CH7521A is designed to meet the DisplayPort specification version 1.2 and the Embedded DisplayPort Specification version 1.2. The 4 Main Link Lanes receiver supports input with data rate running at 1.62Gb/s, 2.7Gb/s or 5.4Gb/s, and can accept digital RGB signal for LVDS output up to 7680x1080@60Hz or 4800x2160@60Hz.

The CH7521A will convert the DisplayPort signal to LVDS output after DisplayPort Link Training is completed. This feature can be achieved by loading the panel’s EDID and the CH7521A’s configuration settings in the serial external BOOT ROM connected to the CH7521A. During system power-up and upon completion of the DisplayPort Link Training through AUX Channel, CH7521A will generate LVDS signal according to the panel power-up timing sequencing stored in the external BOOT ROM.

Advanced Region CRC checking and signal failure detection module and the related interrupt mechanism is incorporated in CH7521A, which is specially designed to reduce the risk of signal transmission error in normal consumer or industrial operation.

结构图

数据表

View the CH7521A Brief Datasheet Rev 0.9

应用说明

PCB Layout and Design Guide for CH7521A, AN-B059 rev0.1

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