CH7111A

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特征



l Compliant with HDMI specification version 2.1

l Supports up to HDMI 12Gbps FRL data rate

l Supports up to HDMI 6Gbps TMDS data rate or 600 MHz TMDS clock for video transport

l Dedicated PLL for removing the jitter of TMDS clock and data, integrated CDR for removing the jitter of FRL signal

l DP++ support in AC coupling input mode for HDMI level shifter

l DC coupling input mode support for HDMI signal retiming

l Automatic link training for FRL mode

l SCDC (Status and Control Data Channel) interception supported

l Adaptive equalizer to compensate for HDMI cables, PCB layout and/or connector losses, and supports up to 34 dB boost at 600MHz

l Configurable Pre-Emphasis on output driver

l 3.3 and 1.2V Power supply

l Crystal-free

l IIC-over-AUX transaction supported

l Active DDC buffer and related control register integrated

l HDMI Identifier supported

l IIC serial port for configuration and chip debugging

l Low power architecture

l RoHS compliant and Halogen free package

l HBM 4KV ESD performance

l Offered in 48-Pin QFN package (6 x 6 mm)

 


 


描述

     Chrontel’s CH7111A is an innovative, low-power, high performance HDMI re-timing semiconductor device for improving the input TMDS/FRL signal to meet the HDMI 2.1 signal integrity requirement. This device integrates adaptive equalizer, receiver CDR, internal oscillator, high performance PLL and configurable Pre-Emphasis module, and is specially designed targeting for the HDMI 2.1 repeater and the DP++ adaptor market segments.

     A sophisticated active DDC buffer is also employed by CH7111A to improve the stability and increase robustness of the HDMI DDC communication

结构图

数据表

应用说明

 PCB Layout and Design Guide for CH7111A, AN-B057 rev0.1

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